Checking date: 28/06/2021


Course: 2021/2022

Computer Organization
(13885)
Study: Bachelor in Computer Science and Engineering (218)


Coordinating teacher: CASTILLO MONTOYA, JOSE CARLOS

Department assigned to the subject: Department of Systems Engineering and Automation

Type: Electives
ECTS Credits: 6.0 ECTS

Course:
Semester:

Branch of knowledge: Engineering and Architecture



Requirements (Subjects that are assumed to be known)
- Programming (1st course, 1st semester) - Computer Structure (2nd course, 1st semester) - Operating Systems (2nd course, 2nd semester) - Computer Architecture (3rd course, 1st semester)
Objectives
The objective of this course is for the student to learn about the evolution and internal structure of computer architectures and the main factors that influence the performance of a computer. Among the concepts that will be studied in depth are: (i) the necessary conditions for parallelism, (ii) the design of the instruction repertoire, (iii) the microarchitecture of the processor, and (iv) the main internal parallelism techniques that are applied in current processors to improve their performance (caches in the processor, dynamic instruction scheduling, hop prediction, superscalarity). Finally, superscalar, supersegmented and VLIW machines will be discussed as an evolution of processors searching for a higher degree of instruction-level parallelism. In terms of capabilities, these can be classified into two groups, one of the specific capabilities and the other of more generic abilities or skills. In terms of specific capabilities, at the end of the course, the student will be able to: - Understand the operation of a basic segmented processor. - Analyse the dependencies existing in a particular code and their effect on processing. - Understand the operation and limitations of existing processors and lines of improvement. - Interpret performance data obtained from the execution of a code on a machine. In terms of general capabilities or skills, the course will focus on the following: - Overview of the complex problem of instruction execution on a segmented processor. Ability to design and carry out code optimisation experiments and organise, analyse, and interpret the results. This ability will be worked on, especially in the laboratory sessions and the resolution and discussion of case studies. - Ability to work in a team in a cooperative, critical and respectful way with the solutions proposed by others.
Skills and learning outcomes
Description of contents: programme
The program is composed by the following items: 1. Introduction to computation in parallel. Concept of parallelism and historic evolution. 2. General organization of a computer. 3. Conditions for the parallelism and analysis of the abilities. Analysis of dependencies. Levels of parallelism process and size of the grain. Characteristics of the performance. Theory performance models. 4. Segmentation fundaments. Basic concepts about segmentation. Structures for controlling functional segmented units. 5. Segmented processors. Basic stages of a segmented processor with a static instructions planning. Types of risks and their possible solutions. Multicicle performance. Dynamic instructions planning. Dynamic jumps prediction. 6. Superscalar structures, supersegmented and VLIW. Superscalar and supersegmented processor concept. Uses of a superscalar processor and of supersegmented ones. VLIW processors.
Learning activities and methodology
1. Theory classes. Presentation of the main concepts. Discussion and clarification of doubts about the concepts. We will work on transparencies that will be given to students to facilitate learning and a text or basic reference texts required in the course. (2,5 ECTS) 2. Classes of practical exercises. Sessions in which problems are posed, and students are left in groups to present their solutions. (2,5 ECTS) 3. Laboratories. Students (in small teams) will be offered practical case studies, and they should study them and then take the simulation data and analyze it. Knowledge of the topics covered in masterclasses and practical classes in the subject will be used. A preliminary study will be carried out, work will be carried out in the laboratory, and a written report will be delivered with the results and proposed solutions. (1 ECTS)
Assessment System
  • % end-of-term-examination 0
  • % of continuous assessment (assigments, laboratory, practicals...) 100
Calendar of Continuous assessment
Basic Bibliography
  • J. L. HENNESSY y D.A. PATTERSON. Computer Architecture: A Quantitative Approach. Fourth Edition. Ed Elsevier 2007.
  • J. SILC et al,. ¿Processor Architecture¿. Springer Verlag, 1999.
Additional Bibliography
  • A.R. OMONDI. The Microarchitecture of Pipelined and Superscalar Computers. Kluwer Academic Publishers, 1999.
  • H. S. STONE. High Performance Computer Architecture. Ed Addison Wesley, 1993.
  • P. M KOGGE. The Architecture of Pipelined Computers. Ed Mc Graw Hill, 1981.

The course syllabus may change due academic events or other reasons.