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Course: 2025/2026

Implementation of Integrated Circuits I

(20090)

Master in Microelectronic Design Engineering (Plan: 546 - Estudio: 410)

EPI

Coordinating teacher: GARCIA VALDERAS, MARIO

Department assigned to the subject: Electronic Technology Department

Type: Compulsory

ECTS Credits: 3.0 ECTS

Course: 1º

Semester: 1º

Requirements (Subjects that are assumed to be known)

It is advisable to have taken or to be taking the following subjects of the master's degree: - Introduction to Microelectronics - Digital Microelectronics - Digital Systems Architecture

Objectives

- To know the manufacturing process and packaging of digital integrated circuits and their physical implementation. - To use simulation and implementation methodologies and tools to design digital integrated circuits. - To evaluate the fulfillment of the requirements of a design or a digital integrated circuit.

Learning Outcomes

Link to document

Description of contents: programme

1. Layout of digital circuits. Physical design of standard digital cells. Implementation based on standard cells. 2. Automatic synthesis: constraints. 3. Place & route: - Floorplanning. Input/output pads - Power distribution - Standard cell placement and routing - Clock tree 4. Post-synthesis and post-layout simulation. 5. Sign-off: - Temporal analysis - Power analysis - Thermal analysis - DRC, LVS, ERC 6. Case study

Learning activities and methodology

- Theoretical class - Practical class - Final exam - Individual work - Group work

Assessment System

The continuous assessment will consist of the development a practical case that will have a weight of 70% of the grade.
The final exam will have a weight of 30% of the grade.

Basic Bibliography

Jan, M. Rabaey, Anantha Chandrakasan and Borivoje Nikoli¿. Digital Integrated Circuits - A Design Perspective (2nd Ed.). Prentice Hall. 2003
Rubio, A. Altet J., Argonés X., González J. L., Mateo D., Moll F.. Diseño de circuitos y sistemas integrados. Universidad Politécnica de Cataluña. 2000
Vaibbhav Taraate. ASIC Design and Synthesis RTL Design Using Verilog. Springer. 2021

Electronic Resources *

Vaibbhav Taraate · ASIC Design and Synthesis RTL Design Using Verilog : https://link.springer.com/book/10.1007/978-981-33-4642-0

(*) Access to some electronic resources may be restricted to members of the university community and require validation through Campus Global. If you try to connect from outside of the University you will need to set up a VPN

The course syllabus may change due academic events or other reasons.